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Digital Design with Verilog® Hdl: (Formerly Titled "Hardware Modeling with Verilog Hdl") (Design Automation Series) Elizer Sternheim 1990 edition
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Digital Design with Verilog® Hdl: (Formerly Titled "Hardware Modeling with Verilog Hdl") (Design Automation Series)
Elizer Sternheim
Verilog HDL is the standard hardware description language for the design of digital systems and VLSI devices. This volume shows designers how to describe pieces of hardware functionally in Verilog using a top-down design approach, which is illustrated with a number of large design examples. The work is organized to present material in a progressive manner, beginning with an introduction to Verilog HDL and ending with a complete example of the modelling and testing of a large subsystem.
| Médias | Livres Paperback Book (Livre avec couverture souple et dos collé) |
| Validé | 5 décembre 1991 |
| ISBN13 | 9780962748806 |
| Éditeurs | Springer |
| Pages | 217 |
| Dimensions | 170 × 244 × 12 mm · 376 g |
| Langue et grammaire | Anglais |
Voir tous les Elizer Sternheim ( par ex. Paperback Book )